The invention relates to an analog-to-digital converter circuit for use in an image sensor chip for converting analog electrical signals into digital signals.
An image sensor is used to convert an optical image focused on the sensor into electrical signals. The image sensor typically includes an array of light detecting elements, where each element produces a signal corresponding to the intensity of light impinging on that element when an image is focused on the array. These signals may then be used, for example, to display a corresponding image on a monitor or otherwise used to provide information about the optical image.
One very common type of image sensor is a charge coupled device (CCD). Integrated circuit chips containing a CCD image sensor have a relatively low yield and are expensive due to the specialized processing involved. The CCDs also consume a relatively large amount of power. Other disadvantages exist.
A much less expensive type of image sensor is formed as an integrated circuit using a CMOS process. In such a CMOS type image sensor, a photodiode or phototransistor (or other suitable device) is used as the light-detecting element, where the conductivity of the element corresponds to the intensity of light impinging on the element. The variable signal thus generated by the light detecting element is an analog signal whose magnitude is approximately proportional (within a certain range) to the amount of light impinging on the element.
It is known to form these light-detecting elements in a two-dimensional core array which is addressable by row and column. Once a row of elements has been addressed, the analog signals from each of the light detecting elements in the row are coupled to the respective columns in the array. An analog-to-digital converter (ADC) may then be used to convert the analog signals on the columns to digital signals so as to provide only digital signals at the output of the image sensor chip.
In many digital-imaging applications, it is desirable to integrate analog-to-digital conversion with an area image sensor. U.S. Pat. No. 5,461,425 by B. Fowler et al. discloses a multi-channel bit-serial analog-to-digital converter (MCBS ADC) architecture that is best suited for converting many input channels simultaneously.
In an MCBS ADC, each input channel contains a one-bit comparator and a one-bit latch. The comparator and the latch are controlled by two external control signals RAMP and BITX, respectively. The two control signals are generated by a single micro-control block and a digital-to-analog (D/A) converter, and they are broadcast to all the input channels. The primary advantage of the MCBS ADC is reflected in its unique architecture, wherein all input channels operate simultaneously for maximum throughput and each input channel has very simple circuitry, i.e., a one-bit comparator and a one-bit latch, for minimum area. In such design the more complicated control circuitry is shared among all input channels so that the overhead of the control circuitry is amortized over many input channels. The MCBS ADC makes it possible to implement digitizing systems with a very large number of input channels, such as an image sensor with pixel-parallel ADCs.
It is realized that, however, this circuitry structure (one-bit comparator and a one-bit latch for each input channel) is still not simple enough for some applications. For instance, in an image sensor with pixel-parallel ADCs (also known as a DPS image sensor) each input channel is a pixel, and each pixel has a very limited amount of area. In this case, even a one-bit comparator and a one-bit latch may take too much area to be implemented cost effectively.
What is desired is to reduce further the input channel structure so that the MCBS ADC can be useful in applications with the most stringent area requirement on input channels, e.g. a CMOS image sensor with small pixel size.
A multi-channel bit-serial analog-to-digital converter architecture with reduced channel circuitry is described herein, in which a one-bit comparator circuit is split between a first part that is associated with each input channel and a second part that is formed external to the input channels. The one-bit latch is also formed external to the input channels. The external part of the comparator and the one-bit latch are shared by a plurality of input channels.
In one embodiment of the invention, a two-dimensional sensor array of pixel elements is fabricated in an integrated circuit. Each of the pixel elements is an input channel which comprises a photodetector and the front-end part of the one-bit comparator. The external part of the comparator and the one-bit latch are built in the periphery of the sensor array and are shared by each column of pixel elements. Because the transistor count in each pixel is dramatically reduced, the area requirement for implementing the pixel elements is hence relaxed.
In another embodiment, by connecting the output of an inverter to the control signal terminal of the comparator, the comparator can be used as a buffer for analog readout. This basically creates an analog read port with a minimum amount of circuitry increase. Sometimes the resulting operational amplifier can be unstable because of the feedback between a comparator""s output and the negative terminal of the comparator. This problem is preferably resolved by designing the comparator as an operational amplifier from the beginning and using only the first stage of the comparator for feedback. In such design, a single stage is inherently stable.